This invention relates to a conductivity modulation type semiconductor device of a four-layer structure having a region on the drain electrode side of an insulated gate, vertical double-diffused metal oxide semiconductor field effect transistor (VDMOSFET), the conductivity type of which is opposite to that of the drain region.
The semiconductor device of this type is obtained by forming an N.sup.- type drain region, by a vapor growth method, on a P type semiconductor layer and forming by a diffusion method in the drain region a region of one conductivity type (hereinafter referred to as a P type body region) and a region having a conductivity type opposite to said one conductivity type and acting as a source region.
Furthermore, it is also known that an N.sup.+ type thin layer is formed between the P type semiconductor layer and the N.sup.- type drain region so as to improve the semiconductor characteristic. In such a semiconductor device an N.sup.+ type layer-like region is formed by the vapor growth method on a P type semiconductor region and then an N.sup.- type drain region is formed by the vapor growth method on the surface of the resultant structure.
FIG. 1 is a cross-sectional view showing a conductivity modulation type semiconductor device having said N.sup.+ type layer-like region.
As set forth above, N.sup.+ type thin layer-like region 12 and N.sup.- type drain region 13 are sequentially formed, in that order, on P type semiconductor layer 11 which functions as an anode region. A plurality of separated P type body regions 14 are formed in the drain region. An N type region acting as a source region 15 is formed by the diffusion method in the P type body region 14. Source region 15 and P type body region 14 are formed in the upper surface portion of the drain region such that they are exposed at the surface of the resultant semiconductor substrate. Insulating layer 19 is formed on the exposed surface area of the semiconductor substrate such that both the end portions of insulating layer 19 are located, respectively, on source region 15 in P type body region 14 and on source region 15 in adjacent P type body region 14 with gate layer 17 buried in insulating layer 19. The portion of the insulating layer overlying the gate layer is removed to partially expose the gate layer. Gate electrode 18 is formed on the exposed surface of the gate layer, source electrode 21 is formed on the exposed surface of the P type body region and source region and anode electrode 20 is formed on exposed surface of P type semiconductor layer 11. In this way, a conductivity modulation type semiconductor device can be produced.
When a voltage is applied to the gate electrode of the conductivity modulation type semiconductor device, a channel inversion layer is formed at the surface of the P type body region, which turns the semiconductor device ON. As a result, electrons move from the source region through the channel layer into the drain region. When a forward bias is also applied across the anode region and the drain region, holes are injected from the anode region into the drain region. With the device in the ON state, the electrons and holes are injected into the drain region to permit conductivity modulation.
Since in the conventional VDMOSFET only electrons, i.e. majority carriers, are injected into the drain region, a greater resistance occurs in the electron flow if the drain region has a greater thickness or a lower concentration level. Such resistance represents most of the ON resistance.
In the conductivity modulation type MOSFET, the N.sup.- type drain region suffers conductivity modulation, which reveals a very small resistance component. That is, a higher withstand voltage is obtained which produces a smaller ON resistance even when the drain region has a greater thickness or a lower concentration level.
On the other hand, a portion of the minority carriers from the anode region is injected into the drain region where they are stored as excess minority carriers. Even if, in order to turn the MOSFET OFF, the channel is closed with the gate application voltage set at a zero level and thus the flow of electrons is stopped, the MOSFET cannot attain its OFF state until the minority carriers so stored are all moved out of the drain region.
Furthermore, during the period in which the electrons left in the drain region pass through the anode region, a fresh injection of minority carriers from the anode region is induced to lengthen the turn-off time.
However, the effect of the injection of the minority carriers from the anode region into the drain region is reduced due to the presence of the N.sup.+ type thin layer-like region, thus enabling a reduction of the total amount of minority carriers stored in the N.sup.- type drain region. The inventors have found that, when the N.sup.+ type layer-like region is so formed as to have a specific resistance of 1 to 2 .OMEGA..multidot.cm and a thickness of 15 .mu.m, the turn-off time can be reduced to about one-fifth that when no such a thin N.sup.+ type layer-like region is formed. The N.sup.+ type thin layer-like region somewhat increases the ON resistance despite its positive effect. If the N.sup.+ type thin layer-like region is properly controlled in impurity concentration level and in thickness, the increase of the ON resistance can be set within a negligible range and at the same time the turn-off time can be reduced to a greater extent.
In the conductivity modulation MOSFET, the N.sup.+ type layer-like region and N.sup.- type drain region are sequentially formed by the vapor growth method on the P.sup.+ type semiconductor layer. In this vapor growth method, a P type impurity, usually boron, contained in the P type semiconductor layer has a greater possibility of being incorporated in the subsequent vapor growth layer. Where there is a greater difference in concentration level between the N.sup.+ type layer-like region and the N.sup.- type region acting as a drain region, that impurity incorporated in the N.sup.+ type region can be disregarded, but that impurity incorporated in the N.sup.- type region provides an inversion layer. It is therefore possible to provide a concentration profile of EQU P.sup.+ (anode region 11)-N.sup.+ (region 12) EQU -P (inversion layer)-N (drain region 13)
as shown in FIG. 2.
In the conductivity modulation type MOSFET having a source-to-drain withstand voltage of about 500 V and a shorter turn-off time on the order of several microseconds, it is preferred that the specific resistance of the N.sup.- type drain region be 20 to 30 .OMEGA..multidot.cm and that the specific resistance of an N.sup.+ type layer-like region be 1 to 2 .OMEGA..multidot.cm. It is very difficult to form the N.sup.+ type layer-like region and N.sup.- type drain region (having such a concentration difference) by the vapor growth method on the P.sup.+ type semiconductor layer (acting as the anode region) without forming the inversion layer. It is, therefore, nearly impossible to stably mass-produce conductivity modulation type semiconductor devices.